" Vim syntax file
" Language:    VHDL
" Maintainer:  Stephan Hegel <ea273@fen.baynet.de>
" Last change: 1997 May 3
 
" Remove any old syntax stuff hanging around
syntax clear

" This is not VHDL. I use the C-Preprocessor cpp to generate different binaries
" from one VHDL source file. Unfortunately there is no preprocessor for VHDL
" available. If you don't like this, please remove the following lines.
syntax match   cDefine           "^#ifdef[ ]\+[A-Za-z_]\+"
syntax match   cDefine           "^#endif"

:syntax case ignore

" VHDL keywords
syntax keyword vhdlStatement     package body entity architecture component
syntax keyword vhdlStatement     block process of is begin end
syntax keyword vhdlStatement     library use
syntax keyword vhdlStatement     type subtype 
syntax keyword vhdlStatement     generic port in out inout buffer
syntax keyword vhdlStatement     constant variable signal file 
syntax keyword vhdlStatement     transport after 
syntax keyword vhdlStatement     function procedure return exit 
syntax keyword vhdlStatement     wait on for until
syntax keyword vhdlStatement     record array access new attribute
syntax keyword vhdlStatement     assert report severity note 
syntax keyword vhdlStatement     failure warning error

" Predifined VHDL types
syntax keyword vhdlType          bit bit_vector
syntax keyword vhdlType          character boolean integer time real
syntax keyword vhdlType          string severity_level
" Predifined standard ieee VHDL types
syntax keyword vhdlType          natural
syntax keyword vhdlType          line text
syntax keyword vhdlType          std_logic std_logic_vector 
syntax keyword vhdlType          std_ulogic std_ulogic_vector
" Predefined non standard VHDL types for Mentor Graphics Sys1076/QHDL 
syntax keyword vhdlType          qsim_state qsim_state_vector 

syntax keyword vhdlConditional   if then elsif else
syntax keyword vhdlConditional   case when others

syntax keyword vhdlRepeat        for loop while to downto
syntax keyword vhdlRepeat        generate

" array attributes
syntax match   vhdlAttribute     "\'high"
syntax match   vhdlAttribute     "\'left"
syntax match   vhdlAttribute     "\'length"
syntax match   vhdlAttribute     "\'low"
syntax match   vhdlAttribute     "\'range"
syntax match   vhdlAttribute     "\'reverse_range"
syntax match   vhdlAttribute     "\'right"
" block attributes
syntax match   vhdlAttribute     "\'behaviour"
syntax match   vhdlAttribute     "\'structure"
" signal attributes
syntax match   vhdlAttribute     "\'active"
syntax match   vhdlAttribute     "\'delayed"
syntax match   vhdlAttribute     "\'event"
syntax match   vhdlAttribute     "\'last_active"
syntax match   vhdlAttribute     "\'last_event"
syntax match   vhdlAttribute     "\'last_value"
syntax match   vhdlAttribute     "\'quiet"
syntax match   vhdlAttribute     "\'stable"
syntax match   vhdlAttribute     "\'transaction"
" type attributes 
syntax match   vhdlAttribute     "\'base"
syntax match   vhdlAttribute     "\'high"
syntax match   vhdlAttribute     "\'left"
syntax match   vhdlAttribute     "\'leftof"
syntax match   vhdlAttribute     "\'low"
syntax match   vhdlAttribute     "\'pos"
syntax match   vhdlAttribute     "\'pred"
syntax match   vhdlAttribute     "\'rightof"
syntax match   vhdlAttribute     "\'succ"
syntax match   vhdlAttribute     "\'val"

syntax region  vhdlString        start=+"+  end=+"+
syntax match   vhdlString        "\'[A-Za-z0-9 ]\'"
syntax match   vhdlVector        "\'[0L1HXWZU\-\?]\'"
syntax keyword vhdlBoolean       true false
syntax match   vhdlTime          "[0-9]\+[ ]\+fs"
syntax match   vhdlTime          "[0-9]\+[ ]\+ps"
syntax match   vhdlTime          "[0-9]\+[ ]\+ns"
syntax match   vhdlTime          "[0-9]\+[ ]\+us"
syntax match   vhdlTime          "[0-9]\+[ ]\+ms"
syntax match   vhdlTime          "[0-9]\+[ ]\+sec"
syntax match   vhdlTime          "[0-9]\+[ ]\+hr"
syntax match   vhdlTime          "now"
syntax match   vhdlPointer       "null"

syntax match   vhdlComment       "--.*$"
syntax match   vhdlNumber        "\<[0-9]\+'[bdh][0-9a-fA-F]\+\>"
syntax match   vhdlNumber        "\<[0-9]\+\>"
syntax match   vhdlGlobal        "\<\$[a-z]\+\>"
syntax match   vhdlOperator      "[&|~><!)(#%@+=?:;,.\^\-*\[\]///////]"
syntax keyword vhdlOperator      and
syntax keyword vhdlOperator      nand
syntax keyword vhdlOperator      or
syntax keyword vhdlOperator      nor
syntax keyword vhdlOperator      xor
syntax keyword vhdlOperator      mod
syntax keyword vhdlOperator      rem
syntax keyword vhdlOperator      abs
syntax keyword vhdlOperator      not


if !exists("did_vhdl_syntax_inits")
  let did_vhdl_syntax_inits = 1
  " The default methods for highlighting.  Can be overridden later

  highlight link cDefine         Special
  highlight link vhdlConditional vhdlStatement
  highlight link vhdlRepeat      vhdlStatement
  highlight link vhdlStatement   Statement
  highlight link vhdlCharacter   Character
  highlight link vhdlString      String
  highlight link vhdlVector      String
  highlight link vhdlBoolean     String
  highlight link vhdlComment     Comment
  highlight link vhdlNumber      String 
  highlight link vhdlTime        String 
  highlight link vhdlPointer     String 
  highlight link vhdlType        Type
  highlight link vhdlOperator    Type
  highlight link vhdlGlobal      Error
  highlight link vhdlAttribute   Type
endif

